R. Garg, S. Khatri,
"Efficient Analytical Determination of the SEU-induced Pulse Shape,"
IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC) 2009, Yokohama, Japan, Jan 19-22 2009, pp. 461-467.
Single event upsets (SEUs) have become problematic for both
combinational and sequential circuits in the deep sub-micron era
due to device scaling, lowered supply voltages and higher operating
frequencies. To design radiation tolerant circuits efficiently,
techniques are required to analyze the effects of a radiation
particle strike on a circuit early in the design flow, and hence
evaluate the circuit's resilience to SEU events. For an accurate
estimation of the SEU tolerance of a circuit, it is important to
consider the effects of electrical masking. This is typically done
by performing circuit simulations, which are slow. In this paper,
we present an analytical model for the determination of the shape
of radiation-induced voltage glitches in combinational circuits.
The output of our approach can be propagated to the primary outputs
of the circuit using existing tools, thereby modeling the effects
of electrical masking. This enables an accurate and quick
evaluation of the SEU robustness of a circuit. Experimental results
demonstrate that our model is very accurate, with a very low root
mean square percentage error in the estimation of the shape of the
voltage glitch of (4.5%) compared to SPICE. Our model gains its
accuracy by using a non-linear model for the load current of the
gate, and by considering the effect of tβ on the radiation induced
voltage glitch. Our analytical model is very fast (275 x faster
than SPICE) and accurate, and can therefore be easily incorporated
in a design flow to estimate the SEU tolerance of circuits early in
the design process. © 2009 IEEE.
Associated Project(s):SHIELD (Smuggled HEU Interdiction through Enhanced anaLysis and Detection): A Framework for Developing Novel Detection Systems Focused on Interdicting Shielded HEU