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Y. Yang, H. Deshpande, G. Choi, P. Gratz, "Exploiting Path Diversity for Low-Latency and High-Bandwidth with the Dual-Path NoC Router," IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea, 20-23 May 2012.


Networks-on-Chips are gaining in popularity as replacement for shared medium interconnects in chip-multiprocessors (CMPs) and multiprocessor systems-on-chips (MPSoCs), their performance becoming essential to system performance. We propose the dual-path router architecture that efficiently exploits path diversity to attain low latency and high throughput without significant hardware overhead. By 1) doubling the number of injection and ejection ports, 2) splitting packets into two halves, 3) recomposing routing policy to support path diversity, and 4) provisioning the network hardware design, we can significantly improve network resource utilization to achieve much higher throughput and lower latencies. Results show that the proposed dual-path router improves 29% saturation bandwidth on uniform random synthetic traffic, while achieving a reduction in average packet latency of 31% and 17% for uniform random synthetic traffic and video benchmarks respectively.

Associated Project(s):

  • SHIELD (Smuggled HEU Interdiction through Enhanced anaLysis and Detection): A Framework for Developing Novel Detection Systems Focused on Interdicting Shielded HEU

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